Cache Simulator

Description:

Cache Simulator done in Python. Four different cache configurations were simulated to output detailed step-by-step information and hit or missed targets. Cache Configurations:

• (N=1, S=1, b=64) a simplest cache, with only 1 block, size of 64 B
• (N=1, S=4, b=16) a Direct Map cache with 4 sets, block size of 16 B
• (N=4, S=1, b=16) a 4-way Fully Associative cache, cache, block size of 8 B [LRU]
• (N=2, S=4, b=8) a 2-way 4-set, Set Associative cache, block size of 8 B [LRU]

Program Includes:

• Detailed step-by step information of memory breakdown (tag, valid bit, offset), LRU (least recently used) information, and hit/miss results
• Contains 8 registers, 256 Bytes of data memory, and functional PC logic for execution
• Outputs data memory and instruction statistics (total, alu, jump, memory, and other instructions)
• Nine custom instructions developed for our CPU

Leveraged Knowledge

• Assembly of CPU under ASIC conditions
• Two modes: Fast Mode (output only hit/miss results), Detailed Mode (output step-by-step cache attempt information and hit/miss results

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