Adder Design Implementations using Quartus II and Design Vision

Description:

The project uses Divide & Conquer strategies learned in lecture to design three different adders at numerous stages. The first stage of the project required to generate design ideas and create proper documentation. The second stage of the project was implementation in Quartus II CAD software. The final stage was to determine delay among the components of the adder using Quartus II Waveform and Area & Delay Analysis on System Vision (conversion of .qar to VHDL). Analysis of each component and delay are documented in the group report.

Program Includes:

• Adders designed: 64-Bit CSA (Carry Select Adder), 64-Bit RCA (Ripple Carry Adder), 8-Bit ACL (Add-carry-later adder, custom design), 16-Bit ACL (32-bit and 64-bit were unsuccessful)
• All components generated from the ground up at minimum level of logic gates

Leveraged Knowledge

• Use of Quartus II and System Vision (area & delay analysis)
• SSH to dedicated ECE server
• Implementation of logic from ground up to develop working design

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